Super Finsim 9.3.58 Linux
Super-FinSim is the top of the line FinSim Verilog simulator. Ever since
the first FinSim Verilog simulator has been sold in 1993, the FinSim
Verilog simulators have introduced many new features that have become
state of the art in Verilog simulation: mixed Compiled and Interpreted
simulation, simulation Farm that allows one engineer to manage hundreds
of simultaneous simulations, separate and incremental compilation, high
performance save and restart, direct integration with C code without the
need for PLI, etc.
Super FinSim supports the entire Verilog standard IEEE 1364-1995 and
many features of IEEE 1364-2001, which are listed under Support for
Verilog 2001. It's support includes SDF, VCD, PLI, as well as excellent
integration with other tools such as a tight integration via API (for
better performance than PLI integration) with Debussy and Verdi debug
environments from Novas Software, and excellent PLI integrations with
Specman from Verisity and Vera from Synopsys for test benches, MMAV from
Denali for memory models, Undertow from Veritools for debug environment,
HDLScore from Summit Design for code coverage, and others.
In the DA Solution Limited `96 benchmark, the predecessor of
Super-FinSim, FinSim-ECS, was rated the fastest Verilog simulator.
FinSim was rated the fastest PC-based Verilog simulator in the ASIC &
FileSize: 24.1 MB